1. The Field of the Invention
The present invention relates to electronic bus transactions as applied to computing systems. More specifically, the present invention relates to methods and associated structure for enabling transfer of burst transactions from a first device to a second device where the burst transactions have an indefinite burst length.
2. Discussion of Related Art
In present electronic computing system designs, it is common for systems to include a bus structure for exchanging information between devices coupled to the bus. More particularly, controlling devices (often referred to as masters or initiators) often transact information with other devices (often referred to as slaves or targets) for purposes of exchanging information. For example, a microprocessor may interact with a memory subsystem for storage and retrieval of data and programmed instructions. Or, for example, a microprocessor or DMA controller may initiate bus transactions to transmit or receive information to, or from, an I/O controller coupled to the bus.
Is also generally known in such electronic systems that burst transactions on the bus improve overall system performance. A burst transactions is one in which, after acquiring control of the bus, a master device initiates a transaction where multiple units of data are transferred in rapid succession during one transaction process on the bus. In other words, rather than each transaction transferring a single unit of data between a first and second device, a burst transaction acquires the bus and transfers a plurality of units of data during the duration of the single burst bus transactions.
Typically, as presently practiced in the art, a burst transaction has some predefined length measured in units of data. The initiating device on the bus acquires control of the bus and applies signals to the bus indicating the predetermined length of the burst transaction. Present systems also provide for burst transactions having any indefinite length. In other words, a master device acquires the bus and provides a burst transaction having no predetermined length. Rather, other signals on the bus are used to indicate termination of the burst transaction.
It is common in the art to utilize bus bridge devices that couple data signals from one bus to another bus. In such environments, it is common to transfer the burst transaction first to the bus bridge device (functioning as a slave or target device) and then forwarding the burst transaction through the bus bridge (acting as a master or initiator on the second bus) to the second bus for processing by an identified slave device.
Devices other than bus bridges may need to forward signals from a device on a first bus to signals on a second bus. For example, a slave device on a first bus may receive signals from a master device on that first bus and forward the signals to a device controller (i.e., I/O device controller) over a second bus unique to the device architecture. Or, for example, a memory controller device may receive signals on a first bus from a master device (i.e., a CPU or DMA controller) and translate and forward those signals to a different bus structure used to control memory devices. In such cases, a burst bus transaction on the first bus must be translated in some manner to corresponding burst transactions on the second bus structure.
As used herein, “bridge” refers to any such devices that adapt signals received on a first bus to signals applied or forwarded by the bridge to a second bus. Such devices include circuits commonly referred to as “bus bridges” but may also include other similar devices as noted above.
Transfer of a burst transaction from one device to another device for further processing is easily performed where the burst transaction has a predetermined length. Information regarding the burst transaction including the predetermined length is simply transferred between devices and the receiving device can process the transaction as required (i.e., forward the transaction on a second bus to an intended target or slave device). However, where a burst transaction has no predetermined length but rather has an indefinite length, problems arise in attempting to transfer the transaction to another device. In particular, it is problematic to transfer such a burst transaction through a bus bridge device or other devices that couple and adapt signals between a first bus and a second bus.
Exemplary of an environment giving rise to this problem is an AMBA AHB bus architecture system. It is common in such architectures to include a bus bridge device to adapt the high-performance AHB bus signals to lower speed buses used for transacting with I/O peripheral devices. Or a first AHB bus may be bridged to a second AHB bus such that the two buses generally avoid contention problems but may access devices on either bus. It is therefore a problem in such an AMBA bus environment to transfer burst transactions of indefinite length through a bus bridge device.
Another exemplary environment giving rise to these problems is a slave device coupled to a first bus (such as an AMBA AHB bus) that receives signals intended for a device controller coupled to the slave device. The slave device, much as a bus bridge functions, converts and forwards those signals to the device controller on a second bus adapted specifically for transactions involving the device.
It is evident from the above discussion that a need exists for an improved architecture to permit transfer of indefinite length burst transactions between devices on a high-performance system.